PXIe-4154
任何PFI引脚都可以从外部输入WFTRIG信号，该信号可作为PFI6/WFTRIG引脚的输出。作为输入，WFTRIG配置为边缘检测模式。您可以选择任何PFI引脚作为WFTRIG的源，并配置上升沿或下降沿的极性选择。WFTRIG的选定边缘开始DAC的波形生成。如果选择内部生成的更新*，则会启动更新间隔计数器（UI）。作为输出，WFTRIG反映启动波形生成的触发器，即使波形生成是由另一个PFI外部触发的。输出为有源高脉冲，脉冲宽度为25至50 ns。该输出在启动时设置为高阻抗。图4-22和4-23显示了WFTRIG的定时要求。图4-22：。WFTRIG输入信号定时图4-23。WFTRIG输出信号定时上升沿极性下降沿极性t w t w=10 ns小t w t w=25-50 ns第4章连接信号©National Instruments Corporation 4-29 NI PCI-6110/6111用户手册更新*信号任何PFI引脚都可以从外部输入更新*信号，该信号可作为PFI5/更新*引脚上的输出。作为输入，在边缘检测模式下配置更新*。您可以选择任何PFI引脚作为更新*的源，并为上升沿或下降沿配置极性选择。选定的更新边*更新DAC的输出。要使用更新*，必须将DAC设置为发布更新模式。作为输出，更新*反映连接到DAC的实际更新脉冲，即使更新是由另一个PFI外部生成的。输出为有效低脉冲，脉冲宽度为50至75 ns。该输出在启动时设置为高阻抗。图4-24和4-25显示了更新*的时间要求。图4-24：。更新*输入信号定时图4-25。更新*输出信号定时DAC在前缘100 ns内更新。用足够的时间分离更新*脉冲，以便新数据可以写入DAC锁存器。除非您选择一些外部源，否则NI PCI-6110/6111UI通常会生成更新*。WFTRIG信号启动UI，软件或内部缓冲区计数器可以停止UI。

Any PFI pin can externally input the WFTRIG signal, which is available as an output on the PFI6/WFTRIG pin. As an input, WFTRIG is configured in the edge-detection mode. You can select any PFI pin as the source for WFTRIG and configure the polarity selection for either rising or falling edge. The selected edge of WFTRIG starts the waveform generation for the DACs. The update interval counter (UI) is started if you select internally generated UPDATE*. As an output, WFTRIG reflects the trigger that initiates waveform generation, even if the waveform generation is being externally triggered by another PFI. The output is an active high pulse with a pulse width of 25 to 50 ns. This output is set to high-impedance at startup. Figures 4-22 and 4-23 show the timing requirements for WFTRIG. Figure 4-22. WFTRIG Input Signal Timing Figure 4-23. WFTRIG Output Signal Timing Rising-edge polarity Falling-edge polarity t w t w = 10 ns minimum t w t w = 25-50 ns Chapter 4 Connecting Signals © National Instruments Corporation 4-29 NI PCI-6110/6111 User Manual UPDATE* Signal Any PFI pin can externally input the UPDATE* signal, which is available as an output on the PFI5/UPDATE* pin. As an input, UPDATE* is configured in the edge-detection mode. You can select any PFI pin as the source for UPDATE* and configure the polarity selection for either rising or falling edge. The selected edge of UPDATE* updates the outputs of the DACs. In order to use UPDATE*, you must set the DACs to posted-update mode. As an output, UPDATE* reflects the actual update pulse that is connected to the DACs, even if the updates are being externally generated by another PFI. The output is an active low pulse with a pulse width of 50 to 75 ns. This output is set to high-impedance at startup. Figures 4-24 and 4-25 show the timing requirements for UPDATE*. Figure 4-24. UPDATE* Input Signal Timing Figure 4-25. UPDATE* Output Signal Timing The DACs are updated within 100 ns of the leading edge. Separate the UPDATE* pulses with enough time that new data can be written to the DAC latches. The NI PCI-6110/6111UI normally generates UPDATE* unless you select some external source. The WFTRIG signal starts the UI, and the UI can be stopped by software or the internal Buffer Counter.