PXIe-4353
定时和同步质量
PXI系统的一个关键优势是集成的定时和同步功能。PXI机箱
集成了专用的10 MHz系统参考时钟、PXI触发总线、星形触发总线和插槽到插槽
本地总线，而PXI Express机箱添加了100 MHz差分系统时钟、差分信号、，
和差分星形触发器，以满足定时和同步的需要。
图8：。PXI Express背板信号布线图
背板系统参考时钟的相位噪声和稳定性是
PXI机箱，因为它们表明您可以期望在系统内同步模块的可靠性。
在选择组件和背板设计的情况下，PXI Express 100的相位噪声性能
NI PXI Express机箱上的MHz差分系统时钟性能比
同类其他供应商的机箱。
您可以将10 MHz和100 MHz系统参考时钟进行锁相环（PLL）以获得更高的稳定性
时钟源，而不是机箱背板上提供的时钟源。这有助于提高PXI的采样率
模块，以便更好地跨多个仪器对齐其样本。NI PXI机箱的PLL电路
设计用于在锁定到外部参考时抑制更多噪音，从而允许更干净
传输更高稳定性的时钟源。使用其他供应商的机箱，具体取决于系统
应用程序所需的时钟源相位噪声，可能需要外部参考锁相
单独时钟到每个模块，而不是在系统级时钟到机箱背板，导致
系统复杂性和成本增加。6.

Timing and Synchronization Quality A key advantage of a PXI system is the integrated timing and synchronization capabilities. A PXI chassis incorporates a dedicated 10 MHz system reference clock, PXI trigger bus, star trigger bus, and slot-to-slot local bus, while a PXI Express chassis adds a 100 MHz differential system clock, differential signaling, and differential star triggers to address the need for advanced timing and synchronization. Figure 8. PXI Express backplane signal routing diagram The phase noise and stability of the backplane system reference clocks are important characteristics of the PXI chassis, as they indicate how reliably you can expect to synchronize modules within the system. Given the choice of components and backplane design, phase noise performance of the PXI Express 100 MHz differential system clock on NI PXI Express chassis has performed orders of magnitude better than other vendors’ chassis in the same class. You can phase-lock-loop (PLL) the 10 MHz and 100 MHz system reference clocks to a higher stability clock source than that which is provided on the chassis backplane. This helps higher-sample-rate PXI modules to better align their samples across multiple instruments. The PLL circuitry of the NI PXI chassis is designed to suppress more noise when locking to an external reference, thus permitting cleaner transmission of the higher stability clock source. With other vendors’ chassis, depending on the system clock source phase noise required by the application, you may need to phase-lock the external reference clock to each module individually rather than at a system level to the chassis backplane, resulting in an increase in system complexity and cost.6